Often, interconnect paths in radio frequency integrated circuits (RFICs) contribute undesirably large inductance due to the path lengths and line widths that are practically available. This large inductance can lead to low circuit performance. For example, an input signal providing a driving current to an RF power amplifier is desired to flow uniformly to each of the cells in an output stage array of cells. Non-uniformity in amplitude and/or phase across the array of cells can cause degradation in power efficiency, gain, and linearity. According to one conventional approach, a single metal layer over a dielectric stack that includes the semiconductor substrate (such as GaAs) is used to interconnect an input to an input terminal of each cell.
Another problem with RFICs is the problem of maintaining a uniform harmonic termination at the output terminal of each cell in an RF power amplifier output stage that is comprised of many individual transistor cells. According to one conventional approach, a single metal layer over a dielectric stack that includes the semiconductor substrate (such as GaAs) is used to interconnect the output terminal of each cell. Harmonic tuning will vary across the cell array due to differing path lengths. The harmonic tuning becomes more difficult as the path length, and correspondingly the inductance difference, between cells in the array and the harmonic tuning resonator accumulates.
There is desired an improved interconnect method for RF integrated circuits that provides a low inductance path between circuit elements at different physical locations. An example of this is the reduction of inductance at the input of an array of cells that are intended to operate in-phase and with equal amplitude. Another example is the desire to reduce interconnect inductance differences between, each transistor cell in an array, and a common harmonic tuning resonator.